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	<title>Big-Endian &#8211; richliu&#039;s blog</title>
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		<title>ARM11 BE8 and BE32</title>
		<link>https://blog.richliu.com/2010/04/08/907/arm11-be8-and-be32/</link>
					<comments>https://blog.richliu.com/2010/04/08/907/arm11-be8-and-be32/#respond</comments>
		
		<dc:creator><![CDATA[richliu]]></dc:creator>
		<pubDate>Thu, 08 Apr 2010 02:21:07 +0000</pubDate>
				<category><![CDATA[ARM]]></category>
		<category><![CDATA[ARM11]]></category>
		<category><![CDATA[BE32]]></category>
		<category><![CDATA[BE8]]></category>
		<category><![CDATA[Big-Endian]]></category>
		<guid isPermaLink="false">http://blog.richliu.com/?p=907</guid>

					<description><![CDATA[<p>What’s difference between BE8 and BE32? BE-32 is suppor [&#8230;]</p>
<p>The post <a rel="nofollow" href="https://blog.richliu.com/2010/04/08/907/arm11-be8-and-be32/">ARM11 BE8 and BE32</a> appeared first on <a rel="nofollow" href="https://blog.richliu.com">richliu&#039;s blog</a>.</p>
]]></description>
										<content:encoded><![CDATA[<p>What’s difference between BE8 and BE32?</p>
<p><span id="more-907"></span></p>
<p>BE-32 is supported by ARM cores up to the ARM11 family (v6) (for example ARM7TDMI, ARM926EJ-S, ARM1136JF-S). It is enabled by setting a bit in the CP15 system control coprocessor.</p>
<p>BE-8 is supported by the ARM11 family and later (for example ARM1136JF-S, Cortex-R4, Cortex-A8). Architecture v7 cores do not support BE-32.</p>
<p>It is controlled by setting a bit in the CPSR.</p>
<p>Setting both bits is reserved (not a valid configuration).</p>
<p>In terms of data access:</p>
<p>BE-8 is byte invariant endianness</p>
<p>BE-32 is word invariant endianness</p>
<p>This is easiest to see with examples. I&#8217;ve starred **** the important ones:</p>
<p>Basic endianness:</p>
<p>Consider a word stored 0x11223344 where 11 is the most significant byte.</p>
<p>Little endian:</p>
<p>Address    0    1    2    3</p>
<p>Data       44   33   22   11</p>
<p>Big endian:</p>
<p>Address    0    1    2    3</p>
<p>Data       11   22   33   44</p>
<p>BE-32 and BE-8</p>
<p>Now consider data stored like this:</p>
<p>Address    0    1    2    3</p>
<p>Data       11   22   33   44</p>
<p>Core in little-endian mode makes word access to address 0:</p>
<p>LDR r0, [0]</p>
<p>r0 contains 0x44332211</p>
<p>Data loaded to register as little endian</p>
<p>Core in little-endian mode makes byte access to address 0:</p>
<p>LDRB r0, [0]</p>
<p>r0 contains 0x00000011</p>
<p>Data loaded from 0</p>
<p>Core in little-endian mode makes byte access to address 3:</p>
<p>LDRB r0, [3]</p>
<p>r0 contains 0x00000044</p>
<p>Data loaded from 3</p>
<p>Core in BE-32 mode makes word access to address 0:</p>
<p>LDR r0, [0]</p>
<p>r0 contains 0x44332211</p>
<p>Word accesses are endianness-invariant</p>
<p>****Core in BE-32 mode makes word access to address 0:</p>
<p>LDRB r0, [0]</p>
<p>r0 contains 0x00000044</p>
<p>Byte access in BE-32 reads the word as if it was stored big-endian</p>
<p>Core in BE-32 mode makes word access to address 3:</p>
<p>LDRB r0, [1]</p>
<p>r0 contains 0x00000011</p>
<p>As above</p>
<p>****Core in BE-8 mode makes word access to address 0:</p>
<p>LDR r0, [0]</p>
<p>r0 contains 0x11223344</p>
<p>Data loaded to register as big endian</p>
<p>Core in BE-8 mode makes byte access to address 0:</p>
<p>LDRB r0, [0]</p>
<p>r0 contains 0x00000011</p>
<p>Byte at address 0 is loaded, NOT the byte at address 3</p>
<p>Core in BE-8 mode makes byte access to address 3:</p>
<p>LDRB r0, [3]</p>
<p>r0 contains 0x00000044</p>
<p>Byte at address 3 is loaded.</p>
<p>Essentially BE-32 operates by altering the addresses of memory accesses when accessing subword quantities. This gives the appearances of big endian.</p>
<p>The post <a rel="nofollow" href="https://blog.richliu.com/2010/04/08/907/arm11-be8-and-be32/">ARM11 BE8 and BE32</a> appeared first on <a rel="nofollow" href="https://blog.richliu.com">richliu&#039;s blog</a>.</p>
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